The present invention relates to a DRAM (Dynamic Random Access Memory), and more particularly, to a cell array of the DRAM.
Generally, with the integration of a semiconductor DRAM device, layouts and structures of cell arrays suitable for high integration thereof have been proposed.
A capacitor under bit line (CUB) structure applies to 16 Mb DRAM sizes or smaller, while a capacitor over bit line (COB) structure applies to 64 Mb DRAM sizes or greater.
FIGS. 1a and 1b depict a layout and a sectional view, respectively, showing a cell array of a conventional CUB structure.
As shown in FIGS. 1a and 1b, the CUB structure includes gate lines 2 arranged in rows on a substrate 1, gate insulator layers 2a, a node electrode 3 over and between the gate lines 2 and in contact with the substrate 1, a plate electrode 4 on the node electrode 3 (a capacitor dielectric between the plate electrode 4 and the node electrode 3 is not shown), an insulator layer 5a on the plate electrode 4, the gate insulator 2a, and the substrate 1, and a bit line 5 over and perpendicular to the gate lines 2. The active region is denoted by X.
That is, the CUB structure includes the bit line 5 formed on a capacitor having the node electrode 3 and the plate electrode 4.
In the CUB structure as aforementioned, in order to obtain a capacitor having a sufficient capacitance required for highly integrated DRAMs, the height of the capacitor must be high. However, this causes a problem in that an aspect ratio of a contact hole 6 of the bit line gets higher. This, in turn, causes difficulties in the technology relating to forming a conductive layer into of the contact hole 6 and patterning the bit line 5.
For this reason, a new layout for the cell array has been required for 64M DRAMs.
FIGS. 2a and 2b show a layout and a sectional view, respectively, showing a cell array of a conventional COB structure.
As shown in FIGS. 2a and 2b, the COB structure includes gate lines 11 arranged in a row on a substrate 10, a bit line 12 perpendicular to the gate lines 11 and in contact with the gate insulating layers 11a and the substrate 10, a node electrode 13 in a rectangular form over and between the gate lines 11 and in contact with the substrate 10 and the gate insulating layers 11a, and a plate electrode 14 over the node electrode 13. A dielectric layer 15 is formed between the plate electrode 14 and the node electrode 13.
In the COB structure as aforementioned, since the bit line 12 is formed sooner than the capacitor, the capacitor region may include the bit line 12. As a result, the aspect ratio of the bit line contact hole 16 does not increase even if the height of the capacitor becomes high for high capacitance.
The cell array of the COB structure allows the effective area of the bit line to be incorporated into the capacitor region. It also allows the effective area of the capacitor to increase by increasing the height of the capacitor so that it can be used in a 64M DRAM or a 256M DRAM.
However, the cell array of the COB structure has several problems.
First, it is hard to mass produce DRAM devices using a technology which increases the effective area of the capacitor, because this goes against the prevailing trend of reducing the effective area of the cell in order to achieve a 1G DRAM size or greater.
Second, shrinkage of the node electrode of the capacitor due to the use of a rectangular-shape pattern makes the electrode region of the capacitor smaller than its actual design.
Third, a narrow interval between the bit lines makes parasitic capacitance of the bit lines higher.
Thus, high capacitance of the cell capacitor is required to maintain the capacitance C.sub.S of the cell capacitor and the parasitic capacitance C.sub.B of the bit line, which have certain levels required for the design of the memory cell. However, it is not suitable for highly integrated devices.